The present invention relates generally to integrated semiconductor memory cell capacitors. In particular, the invention relates to methods and structures for fabricating memory cell capacitors incorporating high dielectric constant materials.
A memory cell in an integrated circuit, such as a dynamic random access memory (DRAM) array, typically comprises a charge storage capacitor (or cell capacitor) coupled to an access device such as a Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET). The MOSFET functions to apply or remove charge on the capacitor, thus effecting a logical state defined by the stored charge. The amount of charge stored on the capacitor is proportional to the capacitance, C=k∈0A/d, where k is the dielectric constant of the capacitor dielectric, ∈0 is the vacuum permittivity, A is the electrode area and d is the spacing between the electrodes.
Integrated circuits in general, including DRAMs, are continually being designed more densely in pursuit of faster processing speeds and lower power consumption. As the packing density of storage cells continues to increase, each cell must still maintain a certain minimum charge storage to ensure reliable operation of their memory cell. It is thus increasingly important that capacitors achieve a high stored charge per footprint or unit of chip area occupied.
Several techniques have recently been developed to increase the total charge capacity of the cell capacitor without significantly affecting the chip area occupied by the cell. These techniques include increasing the effective surface area of the electrodes by creating folding structures such as trench or stacked capacitors. Such structures better utilize the available chip area by creating three dimensional shapes to which the conductive electrodes and capacitor dielectric conform. The surface of the electrodes may be further increased by providing a roughened surface to the bottom electrode over which the capacitor dielectric and the top electrode are conformally deposited.
Other techniques concentrate on the use of new dielectric materials having higher dielectric constants (k). Such materials include tantalum oxide (Ta2O5), barium strontium titanate (BST), strontium titanate (ST), barium titanate (BT), lead zirconium titanate (PZT), and strontium bismuth tantalate (SBT). Such materials effectively possess dielectric constants significantly greater than conventional dielectrics (e.g., silicon oxides and nitrides). Whereas k equals 3.9 for silicon dioxide, the dielectric constants of these new materials can range from 20 to 40 (tantalum oxide) to 300 (SBT), and some even higher (600 to 800). Using such materials enables the creation of much smaller and simpler capacitor structures for a given stored charge requirement, enabling the packing density dictated by future generation circuit design.
Difficulties have been encountered, however, in incorporating these materials into fabrication process flows. For example, chemical vapor deposition of PZT and BST is conducted in a highly oxidizing ambient. Polycrystalline silicon capacitor plates are thus subject to oxidation during such deposition. The silicon dioxide formed in polysilicon electrodes has a much lower dielectric constant than the xe2x80x9chigh kxe2x80x9d material, which drastically lowers the overall capacitance of the capacitor. Conventionally, the bottom electrode is first formed, followed by the high k dielectric material and then the top electrode.
To avoid such degradation in capacitance, electrodes can be made of noble metals, such as platinum. Unfortunately, oxygen easily diffuses through platinum electrodes and oxidizes underlying oxidation-susceptible elements, such as active areas of underlying transistors, or polysilicon or tungsten plugs used to contact such active areas. Oxidation of either the electrode or the underlying electrical elements reduces conductivity and slows circuit operation. Furthermore, high dielectric materials typically require an anneal step to cure the high dielectric material, such as by driving out carbon from organometallic precursors. During these high temperature steps, oxidation of adjacent elements reduces the oxygen content in the high dielectric material. If even a small percentage of the oxygen content is lost, highly conductive electrical paths can be formed through the dielectric constant material, leading to unacceptable levels of current leakage and failure of the memory cell.
The diffusion of oxygen through noble metal electrodes has led to the suggestion of using conductive diffusion barriers between the high dielectric material and the underlying polysilicon plug. Such barrier layers, however, have been difficult to integrate into the process flow, and furthermore have a tendency to break down during subsequent processing. Moreover, such conductive barrier layers have a limited width of necessity, since they must be isolated from one another across a memory array. Accordingly, oxygen can still diffuse the relatively short distance around such barrier layers to the underlying substrate or plug.
Thus, a need exists for a capacitor structure and a process flow for integrating high dielectric constant materials into memory cell capacitors. Desirably, such capacitors and process flows should avoid oxidation of underlying oxidizable structures and the chemical or physical breakdown of dielectric material itself.
In the illustrated embodiment, these needs are fulfilled by a process of forming an integrated capacitor whereby a high dielectric constant material is formed prior to formation of the electrodes. Oxidation of the electrodes and oxygen diffusion through the electrodes during dielectric formation is thereby avoided. Moreover, oxygen depletion from the high k material is minimized. The disclosed process flow also enables incorporation of a relatively thick diffusion barrier to prevent oxidation of underlying oxidizable elements, such as polysilicon plugs, during high k material formation.
Thus, in accordance with one aspect of the invention, a process for forming a capacitor in an integrated circuit is provided. The process includes forming an insulative protective layer above a circuit node, and a dielectric layer above the protective layer. After forming the dielectric layer, a first conductive layer is then formed on a first side of the dielectric layer. The first conductive layer is electrically connected to the circuit node through the protective layer.
In accordance with another aspect of the present invention, a method is provided for forming an integrated circuit having a memory cell capacitor. A high k dielectric layer is formed above a semiconductor substrate, which includes a transistor active area. After forming the dielectric layer, a storage electrode is formed, followed by forming a reference electrode.
In accordance with still another aspect of the invention, a process is disclosed for forming a memory cell capacitor in an integrated circuit. The process involves forming an insulating protective layer above a circuit node, and a structural layer above the protective layer. A via is etched into the structural layer, and then lined with a dielectric material having a high dielectric constant, thereby forming a dielectric container. This dielectric container is, in turn, lined with a first conductive layer. A spacer etch then extends through the dielectric container and the underlying protective layer, exposing the circuit node. A second conductive layer is deposited to electrically connect the first conductive layer to the circuit node. Upon removing the structural layer from outside the dielectric container, a third conductive layer is formed outside the dielectric container.
In accordance with still another aspect of the present invention, an integrated circuit is provided with a memory cell capacitor above a semiconductor substrate. An oxidizable conductive plug extends from the substrate to a first level, and an insulating protective layer has a thickness of at least about 500 xc3x85 above the first level. A container-shaped dielectric layer is formed above the insulating protective layer. An inside surface of the dielectric layer is lined with a first conductive layer, while a second conductive layer directly contacts the first conductive layer and extends through the protective layer to electrically contact the conductive plug. A third conductive layer lines an outside surface of the dielectric container.
In accordance with another aspect of the invention, a system having an integrated capacitor over a semiconductor substrate includes an oxidizable circuit node. The system further includes a capacitor dielectric layer characterized by a dielectric constant of greater than about 30. A reference electrode directly contacts one side of the dielectric layer. An oxidation-resistant conductive layer directly contacts both the opposite side of the dielectric layer and the oxidizable circuit node.